Dual loop pll

ABSTRACT

In a dual loop PLL having a frequency comparison loop and a phase comparison loop, when an input control circuit  30  of an up/down counter  8  receives an UP signal from a frequency comparator  7 , the input control circuit  30  outputs a positive value of a ½ of a previous addition/subtraction result value. When the input control circuit  30  receives a DOWN signal from the frequency comparator  7 , the input control circuit  30  outputs a negative value of a ½ of the previous addition/subtraction result value. A register  33  stores a count value. The adder  31  adds the output of the input control circuit  30  to the output of the register  33 . Thus, the up/down counter  8  increments or decrements by a ½ value of the previous addition/subtraction result value, and the dual loop PLL performs a frequency comparison based on a dichotomizing search method. Therefore, even when the output frequency is high, the frequency comparison is efficiently performed, and the lock up time is reduced.

TECHNICAL FIELD

[0001] The present invention relates to a dual loop PLL which includes afrequency comparison loop and a phase comparison loop.

BACKGROUND ART

[0002] Among conventional PLLs (Phase Locked Loops), there has been adual loop PLL which includes a frequency comparison loop and a phasecomparison loop and which achieves phase synchronization over a wideoutput frequency range without increasing the gain of a voltagecontrolled oscillator. This conventional technique is disclosed in, forexample, Yi-Cheng Chang, Edwin W. Greeneich, “MONOLITHIC PHASE-LOCKEDLOOP CIRCUITS WITH COARSE-STEERING ACQUISITION AID” Circuits andSystems, 1999. 42nd Midwest Symposium on Volume: 1, 1999 Page(s):283-286 vol. 1.

[0003] The dual loop PLL is capable of decreasing the gain of a voltagecontrolled oscillator even if the output frequency range is expanded.Thus, the dual loop PLL has the advantage of decreasing the influencewhich is caused by a variation of a voltage input to the voltagecontrolled oscillator and imposed on the oscillation frequency. Further,the dual loop PLL has the function of autonomously correcting thecharacteristics of the voltage controlled oscillator to necessarycharacteristics by a frequency comparison even when the characteristicsof the voltage controlled oscillator are varied due to variations in theproduction process.

[0004]FIG. 13 shows a circuit structure of a conventional dual loop PLL.In FIG. 13, reference numeral 1 denotes a phase comparator, referencenumeral 2 denotes a charge pump, reference numeral 3 denotes anoperation mode switch which switches between the P-side and the F-side,reference numeral 4 denotes a loop filter, reference numeral 5 denotes avoltage controlled oscillator (VCO), reference numeral 6 denotes afrequency divider circuit, reference numeral 7 denotes a frequencycomparator, reference numeral 8 denotes an up/down counter, referencenumeral 9 denotes a VCO characteristic control circuit, referencenumeral 10 denotes external reference clock CLex, reference numeral 11denotes internal clock CLin, reference numeral 15 denotes referencevoltage Vref, reference numeral 16 denotes frequency comparison stopsignal FSTOP, and reference mark OUT denotes an output terminal to whichthe output side of the voltage controlled oscillator 5 is connected.

[0005] Hereinafter, an operation of the dual loop PLL is described withreference to FIG. 13.

[0006] First, in the dual loop PLL, the operation mode switch 3 is seton the F-side, so that a voltage input to the loop filter 4 is referencevoltage Vref (15), and the loop starting from the phase comparator 1 isopen. Thus, the loop is a frequency comparison loop which passes throughthe frequency comparator 7, the up/down counter 8, the VCOcharacteristic control circuit 9, the voltage controlled oscillator 5and the frequency divider circuit 6.

[0007] In the frequency comparison loop, constant reference voltage Vref(15) is supplied as an input voltage to the voltage controlledoscillator 5. The dual loop PLL operates only in a frequency comparisonmode. In the frequency comparison mode, the frequency comparator 7compares the frequency of internal clock CLin (11), which is obtained bydividing the output frequency of the voltage controlled oscillator 5,with the frequency of external reference clock CLex (10). If thefrequency of external reference clock CLex (10) is higher than thefrequency of internal clock CLin (11), the frequency comparator 7outputs an UP signal. If the frequency of external reference clock CLex(10) is lower than the frequency of internal clock CLin (11), thefrequency comparator 7 outputs an DOWN signal. Receiving the UP signalor DOWN signal from the frequency comparator 7, the up/down counter 8adds or subtracts “1” to/from the count value according to the receivedsignal. Receiving a digital output of the up/down counter 8, the VCOcharacteristic control circuit 9 shifts the V-F (input voltage tofrequency) characteristic of the voltage controlled oscillator 5according to the value of the received digital output to change theoutput frequency. As a result, the frequency of internal clock CLin (11)increasingly or decreasingly changes to a frequency closer to that ofexternal reference clock CLex (10).

[0008] The series of operations described above, i.e., a frequencycomparison of external reference clock CLex (10) and internal clock CLin(11), change of the count value of the up/down counter 8 according to aresult of the frequency comparison, and change of the V-F characteristicof the voltage controlled oscillator 5 by the VCO characteristic controlcircuit 9 such that the frequency of internal clock CLin (11) is changedto a frequency closer to that of external reference clock CLex (10), isrepeated until these frequencies becomes substantially equal, and thefrequency comparator 7 outputs frequency comparison stop signal FSTOP(16).

[0009] After the frequency comparator 7 outputs frequency comparisonstop signal FSTOP (16), the count value of the up/down counter 8 isfixed, and the operation mode switch 3 switches from the F-side to theP-side, so that the output side of the charge pump 2 is connected to theinput side of the loop filter 4. As a result, the loop changes to aphase comparison loop which passes through the phase comparator 1, thecharge pump 2, the loop filter 4, the voltage controlled oscillator 5and the frequency divider circuit 6.

[0010] In the phase comparison loop, the phase comparator 1 compares thephase of external reference clock CLex (10) with the phase of internalclock CLin (11). If the phase of external reference clock CLex (10) isfaster than the phase of internal clock CLin (11), the phase comparator1 outputs an UP signal for a time period corresponding to the phasedifference. If the phase of external reference clock CLex (10) is slowerthan the phase of internal clock CLin (11), the phase comparator 1outputs a DOWN signal for a time period corresponding to the phasedifference. The charge pump 2 charges or discharges the loop filter 4according to the UP signal or DOWN signal from the phase comparator 1.The loop filter 4 integrates the charging or discharging operationperformed by the charge pump 2 and converts the integral to a directvoltage, which is employed as an input voltage to the voltage controlledoscillator 5. According to the input voltage, the output frequency ofthe voltage controlled oscillator 5 is changed. The series of operationsdescribed above is repeated until the phase of external reference clockCLex (10) and phase of internal clock CLin (11) are synchronized witheach other, so that the output of the voltage controlled oscillator 5 isa signal (clock) which is synchronized with external reference clockCLex (10) and which has a frequency higher than that of externalreference clock CLex (10) by a factor of N (N is the frequency dividingratio of the frequency divider circuit 6).

[0011] Problems to be Solved

[0012] In the structure of the conventional dual loop PLL describedabove, the up/down counter 8 in the frequency comparison loop changes ona “1”-step by “1”-step basis. For example, when the maximum oscillationfrequency is demanded in the voltage controlled oscillator 5, the countvalue of the up/down counter 8 must be changed to a maximum value. Tothis end, a frequency comparison in the frequency comparator 7 must berepeated 2^(M) times (M is the number of bits of the up/down counter 8).Accordingly, the lock up time of the dual loop PLL increases.

DISCLOSURE OF INVENTION

[0013] The present invention was conceived for the purpose of overcomingthe above problems involved in the conventional techniques. An objectiveof the present invention is to provide a dual loop PLL capable ofefficiently performing a frequency comparison at a high speed.

[0014] For the purpose of achieving the above objective, in a dual loopPLL of the present invention, a frequency comparison is efficientlyperformed based on a dichotomizing search method.

[0015] A dual loop PLL of the present invention comprises: a frequencycomparison loop which includes a frequency comparator and a phasecomparison loop which includes a phase comparator, wherein in thefrequency comparison loop, a frequency comparison between a referencefrequency and an output frequency is performed based on a dichotomizingsearch method.

[0016] According to the present invention, in the dual loop PLL, thefrequency comparison loop includes the frequency comparator, an up/downcounter for incrementing or decrementing a count value according to acomparison result from the frequency comparator, and a voltagecontrolled oscillator for changing the output frequency according to thecount value of the up/down counter; and the up/down counter includes aregister for storing the count value, an input control circuit foroutputting a positive or negative value of a ½ of a previousaddition/subtraction result value according to the comparison resultfrom the frequency comparator, and an adder for adding the count valueof the register to the output of the input control circuit.

[0017] According to the present invention, in the dual loop PLL, thefrequency comparator includes an accuracy varying circuit for varying afrequency comparison accuracy for respective steps of the frequencycomparison along with the progress of the dichotomizing search.

[0018] According to the present invention, in the dual loop PLL, thefrequency comparator is structured such that if the output frequency isequal to or lower than the reference frequency, the frequency comparatoroutputs an UP signal, and if the output frequency is equal to or higherthan the reference frequency, the frequency comparator outputs an DOWNsignal; and the up/down counter includes an error count preventioncircuit for prohibiting an increment or decrement of the count valuewhen the UP signal and DOWN signal are simultaneously received from thefrequency comparator.

[0019] According to the present invention, in the dual loop PLL, thefrequency comparator avoids comparing a transient frequency, whichoccurs during the period when the voltage controlled oscillator controlsa variation in the output frequency, with the reference frequency.

[0020] According to the present invention, in the dual loop PLL, thephase comparison loop includes a voltage controlled oscillator, and aloop filter placed at a stage previous to the voltage controlledoscillator; and when the frequency comparison loop is formed, the loopfilter is disconnected from the voltage controlled oscillator, and areference voltage having a predetermined value is supplied to the loopfilter and the voltage controlled oscillator.

[0021] According to the present invention, in the dual loop PLL, whenthe frequency comparison loop is formed, the voltage controlledoscillator receives a reference voltage having a predetermined value;and the up/down counter includes a priority switch circuit whichreceives a comparison result from the frequency comparator and, if thereference frequency and the output frequency are equal to each other,priorly increments or decrements a count value according to a variationof the reference voltage from the predetermined value.

[0022] According to the present invention, the dual loop PLL furthercomprising: a charge pump placed at a stage subsequent to the phasecomparator; a loop filter which is charged and discharged by the chargepump; and a voltage controlled oscillator to which an input voltage issupplied from the loop filter, wherein in the frequency comparison mode,the charge pump supplies a reference voltage having a predeterminedvalue to the loop filter, and in the phase comparison mode, the chargepump charges or discharges the loop filter according to an output of thephase comparator.

[0023] According to the present invention, in the dual loop PLL, thephase comparison loop includes a charge pump placed at a stagesubsequent to the phase comparator, a loop filter placed at a stagesubsequent to the charge pump; and the loop filter includes a resistorhaving an end connected to the output side of the charge pump, and aN-type transistor and a P-type transistor whose gate terminals areconnected to the other end of the resistor, wherein the N-typetransistor has a source terminal, a drain terminal and a bulk terminalwhich are connected to the ground, and the P-type transistor has asource terminal, a drain terminal and a bulk terminal which areconnected to the power supply.

[0024] Thus, according to the present invention, in a dual loop PLL, thefrequency comparison in a frequency comparison loop is performed basedon a dichotomizing search method. Thus, the frequency comparison isefficiently performed, and the lock up time is effectively reduce, ascompared with a conventional example where an up/down counter changes ona “1”-step by “1”-step manner. For example, in the case where it isnecessary to increase the output frequency up to the maximum frequency,time reduction is possible.

[0025] According to the present invention, when a frequency comparisonis performed based on a dichotomizing search, the absolute value of avariation in the frequency of the voltage controlled oscillator ismoderately decreased on a half-step by half-step basis in the frequencycomparison loop. Thus, the comparison accuracy required of the frequencycomparator can be decreased more at earlier steps of the frequencycomparison. Moreover, the comparison accuracy is varied by an accuracyvarying circuit of the frequency comparator. Thus, the comparisonaccuracy is lower in the earlier steps of the frequency comparisonperformed along with the progress of the dichotomizing search, and thecomparison accuracy of the frequency comparator is optimized for therespective steps of the frequency comparison. As a result, the frequencycomparison time in each step is reduced, and moreover, the lock up timeis reduced.

[0026] According to the present invention, when the output frequencybecomes equal to the reference frequency before the frequency comparisonbased on the dichotomizing method is not completed, the frequencycomparator outputs the UP signal and DOWN signal simultaneously.However, an error count prevention circuit prohibits an up count(increment) or down count (decrement) in the up/down counter. Thus, theerror count is prevented, and at this point in time, the frequencycomparison mode can be ended.

[0027] According to the present invention, the frequency comparatoravoids comparing a transient output frequency with the referencefrequency during the period when the voltage controlled oscillatorcontrols a variation in the output frequency. Thus, the frequencycomparison is always performed with the stable output frequency and thereference frequency, and a desirable frequency comparison is secured.

[0028] According to the present invention, when the frequency comparisonloop is formed, the loop filter is disconnected from the voltagecontrolled oscillator so that a predetermined reference voltage of areference voltage circuit is directly supplied to the voltage controlledoscillator. Thus, the loop filter does not constitute a load, and theload on the reference voltage circuit is reduced. Therefore, it ispossible to quickly adjust the voltage input to the voltage controlledoscillator to the predetermined reference voltage. Moreover, when thefrequency comparison loop is formed, the voltage of the disconnectedloop filter is charged to the predetermined reference voltage. Thus,even when the dual loop PLL transitions from the frequency comparisonloop to the phase comparison loop so that the loop filter is connectedto the voltage controlled oscillator, no variation occurs in the voltageinput to the voltage controlled oscillator, and thus, the lock up timeof the PLL is reduced.

[0029] According to the present invention, when the frequency comparisonloop is formed, if the reference voltage input to the voltage controlledoscillator is lower or higher than the predetermined value, the voltagewhich is input to the voltage controlled oscillator during the PLL beinglocked is lower or higher than the reference voltage having thepredetermined value. However, when a comparison result from thefrequency comparator indicates that the reference frequency and theoutput frequency are substantially equal to each other, a priorityswitch circuit of the up/down counter priorly decrements or incrementsthe count value according to the variation direction of the referencevoltage. Thus, the voltage which is input to the voltage controlledoscillator during the PLL being locked results in a reference voltagesubstantially equal to the predetermined value. Therefore, even when thevoltage value of the reference voltage supplied to the voltagecontrolled oscillator is varied due to variations in the productionprocess, the voltage which is input to the voltage controlled oscillatorduring the PLL being locked is adjusted to an optimum reference voltagehaving the predetermined value.

[0030] According to the present invention, the function of an operationmode switch, which switches the operation mode between the frequencycomparison mode and the phase comparison mode, is realized by a chargepump. Thus, it is not necessary to provide the operation mode switch.Moreover, the reference voltage required by the loop filter when thefrequency comparison mode is selected is generated by the charge pump.Thus, it is not necessary to provide a reference voltage generationcircuit.

[0031] According to the present invention, in the loop filter, a leakedcurrent flowing from a N-type transistor, which may occur in the powerdown mode, is cancelled by a leaked current flowing from a P-typetransistor, which is connected to the power supply, to the N-typetransistor. Thus, the potential of the loop filter is maintained at asubstantially constant potential for a long time period. Therefore,after the PLL transitions from the power down mode to the normaloperation, locking of the PLL can be achieved within a short time periodas compared with conventional loop filters. Furthermore, since theP-type transistor connected to the power supply is provided in additionto the N-type transistor connected to the ground, a variation in acombined MOS capacitance with respect to a bias voltage is restricted toa small variation.

BRIEF DESCRIPTION OF DRAWINGS

[0032]FIG. 1 shows a circuit structure of a dual loop PLL according toembodiment 1 of the present invention.

[0033]FIG. 2 shows a circuit structure of a clock counter included in afrequency comparator of the dual loop PLL according to embodiment 1 ofthe present invention.

[0034]FIG. 3 shows a circuit structure of an input control circuitincluded in an up/down counter of the dual loop PLL according toembodiment 1 of the present invention.

[0035]FIG. 4 shows a circuit structure of a clock counter included in afrequency comparator of a dual loop PLL according to embodiment 2 of thepresent invention.

[0036]FIG. 5 shows a circuit structure of an input control circuitincluded in an up/down counter of a dual loop PLL according toembodiment 3 of the present invention.

[0037]FIG. 6 shows a circuit structure of a frequency comparatorincluded in a dual loop PLL according to embodiment 4 of the presentinvention.

[0038]FIG. 7 shows a circuit structure of a dual loop PLL according toembodiment 5 of the present invention.

[0039]FIG. 8 shows a circuit structure of an input control circuitincluded in an up/down counter of a dual loop PLL according toembodiment 6 of the present invention.

[0040]FIG. 9 shows a circuit structure of a charge pump included in adual loop PLL according to embodiment 7 of the present invention.

[0041]FIG. 10 shows a circuit structure of the dual loop PLL includingthe charge pump according to embodiment 7 of the present invention.

[0042]FIG. 11(a) shows a circuit structure of a loop filter included ina dual loop PLL according to embodiment 8 of the present invention. FIG.11(b) shows a circuit structure of a loop filter of a conventional dualloop PLL.

[0043]FIG. 12(a) shows a voltage characteristic of MOS capacitance in aloop filter of a dual loop PLL according to embodiment 8 of the presentinvention. FIG. 12(b) shows a voltage characteristic of MOS capacitancein a loop filter of a conventional dual loop PLL.

[0044]FIG. 13 is a block diagram showing a circuit structure of aconventional dual loop PLL.

BEST MODE FOR CARRYING OUT THE INVENTION

[0045] Hereinafter, embodiments of the present invention are describedwith reference to the drawings.

[0046] (Embodiment 1)

[0047]FIG. 1 shows a circuit structure of a dual loop PLL according toembodiment 1 of the present invention. In FIG. 1, reference numeral 1denotes a phase comparator, reference numeral 2 denotes a charge pump,reference numeral 3 denotes an operation mode switch which switchesbetween the P-side and the F-side, reference numeral 4 denotes a loopfilter, reference numeral 5 denotes a voltage controlled oscillator(VCO), reference numeral 6 denotes a frequency divider circuit,reference numeral 7 denotes a frequency comparator, reference numeral 8denotes an up/down counter, reference numeral 9 denotes a VCOcharacteristic control circuit, reference numeral 10 denotes externalreference clock CLex, reference numeral 11 denotes internal clock CLin,reference numeral 12 denotes reset signal NR, reference numeral 15denotes reference voltage Vref, and reference numeral 16 denotesfrequency coincidence signal FSTOP.

[0048] In the frequency comparator 7, reference numerals 20 and 21denote clock counters, reference numeral 22 denotes a OR circuit, andreference numeral 23 denotes an AND circuit. In the up/down counter 8,reference numeral 30 denotes an input control circuit, reference numeral31 denotes an adder, reference numeral 32 denotes a selector, andreference numeral 33 denotes a register.

[0049] The phase comparator 1 compares external reference clock CLex(10) and internal clock CLin (11). A result of the comparison, i.e., anUP signal or DOWN signal, is input to the charge pump 2. The operationmode switch 3 has a P-side which is connected to the output side of thecharge pump 2 and a F-side which is connected to reference voltage Vref(15). The operation mode switch 3 switches between the P-side and theF-side under the control of frequency coincidence signal FSTOP (16)output from the up/down counter 8. The loop filter 4 is connected to theoutput side of the operation mode switch 3. The output of the loopfilter 4 is input to the voltage controlled oscillator 5, and thefrequency of the voltage controlled oscillator 5 is changed according tothe voltage input from the loop filter 4. The output frequency of thevoltage controlled oscillator 5 is divided by the frequency dividercircuit 6 to generate internal clock CLin (11).

[0050] Receiving external reference clock CLex (10) and internal clockCLin (11), the frequency comparator 7 compares the frequencies of theseclocks (reference frequency and output frequency) to output a UP signalor DOWN signal as a result signal of the comparison. On the other hand,the frequency comparator 7 is initialized by reset signal NR (12).Receiving frequency coincidence signal FSTOP (16) from the up/downcounter 8, the frequency comparator 7 stops a frequency comparison.Receiving the UP signal or DOWN signal from the frequency comparator 7,the up/down counter 8 updates the count value. The up/down counter 8 isinitialized by reset signal NR (12). The VCO characteristic controlcircuit 9 receives the count value of the up/down counter 8 and controlsthe V-F characteristic of the voltage controlled oscillator 5 based onthe count value.

[0051] Next, the structure of the frequency comparator 7 is described indetail. In the frequency comparator 7, the clock counter 20 countsexternal reference clock CLex (10). The clock counter 20 is reset by theoutput of an AND circuit 23 (described later). Output signal C of theclock counter 20 is an UP signal. The other clock counter 21 countsinternal clock CLin (11). The clock counter 21 is reset by the output ofthe AND circuit 23. Output signal C of the clock counter 21 is a DOWNsignal. The OR circuit 22 receives outputs CKO (described later) fromthe two clock counters 20 and 21. The output of the OR circuit 22 isclock signal CK output from the frequency comparator 7. The AND circuit23 receives reset signal NR (12) and outputs NRO (described later) fromthe clock counters 20 and 21. The output signal of the AND circuit 23 isa reset signal which resets the clock counters 20 and 21.

[0052] The two clock counters 20 and 21 included in the frequencycomparator 7 have the same structure. The internal structure of theclock counter 20 is shown in FIG. 2. In FIG. 2, the clock counter 20includes a counter 40, an AND circuit 41, and a D-type flip flop circuit42. The counter 40 receives external reference clock CLex (10) at a ckterminal 43 and a reset signal from the AND circuit 23 at a NR terminal.The counter 40 counts the received signal in n bits (A₁ to A_(n)). Themost significant bit A_(n) of the counter 40 is output as a C-signal 45.The AND circuit 41 receives the most significant bit A_(n) and the leastsignificant bit A₁ of the counter 40. The output of the AND circuit 41is output CKO (46) of the clock counter 20. The D-type flip flop circuit42 receives output CKO (46) from the AND circuit 41 as a data input. TheD-type flip flop circuit 42 receives external reference clock CLex (10)or internal clock CLin (11), which is input at the CK terminal 43, as aclock input. The output of the D-type flip flop circuit 42 is output NRO(4) of the clock counter 20.

[0053] Next, the internal structure of the up/down counter 8 shown inFIG. 1 is described. In the up/down counter 8 of FIG. 1, the register 33stores a previous count value of the up/down counter 8. The inputcontrol circuit 30 receives the UP signal from the clock counter 20 ofthe frequency comparator 7, the DOWN signal from the other clock counter21 of the frequency comparator 7, and clock signal CK from the ORcircuit 22. The input control circuit 30 has an internal structure shownin FIG. 3. The input control circuit 30 outputs a positive or negativevalue of a ½ value of a previous addition/subtraction result valueaccording to the UP signal or DOWN signal received from the frequencycomparator 7 as described later. The adder 31 adds the output of theinput control circuit 30 to the output of the register 33. The selector32 receives the output of the adder 31 and the output of the register 33and selects one of the received outputs according to the mostsignificant bit of the output of the adder 31 which functions as acontrol signal. The register 33 receives the output of the selector 32and latches the received output of the selector 32 based on clock signalCK received from the OR circuit 22 of the frequency comparator 7.

[0054] Assuming that the count value of the up/down counter 8 has Nbits, the output of the input control circuit 30 and the input andoutput of the adder 31 each have N+1 bits, and the input and output ofthe selector 32 and the register 33 each have N bits. The (N+1)th bit(most significant bit) of the output of the adder 31 is used as a signbit. In this case, the output of the register 33 lacks one bit when itis input to the adder 31. This one bit is compensated for by adding “0”as the most significant bit so that a positive value is always inputfrom the register 33 to the adder 31. The sign bit (the most significantbit of the output of the adder 31) is “1” when the output of the adder31 is OVERFLOW or a negative value.

[0055] The selector 32 receives the sign bit as a control signal. Whenthe sign bit is “1”, the selector 32 selects the register 33 so that theoutput of the register 33 is latched as it is in the register 33,whereby the count value of the up/down counter 8 is prevented fromresulting in a wrong value.

[0056] Referring to FIG. 3, the input control circuit 30 of the up/downcounter 8 includes a state transition circuit 51 having N−1 bit (C₁ toC_(n−1)) outputs, a OR circuit 52, N−1 logic circuits 53, and a D-typeflip flop circuit 54. At a time when the state transition circuit 51 isreset, the most significant bit C_(n−1) is “1” and each of the otherbits is “0”. Thereafter, every time the state transition circuit 51receives clock signal CK from the frequency comparator 7, the mostsignificant bit among the bits outputting “0” transitions to “1”.

[0057] The OR circuit 52 receives the DOWN signal and the UP signal fromthe frequency comparator 7. The logic circuits 53 have the samestructure. Referring to FIG. 3, each logic circuit 53 includes an ANDcircuit 55, a selector 56, and two other AND circuits 57 and 58. The ANDcircuit 55 receives the output of the OR circuit 52 and the DOWN signal.The selector 56 receives the output of the AND circuit 55 and the outputof the OR circuit 52 and operates according to the output of the ANDcircuit 58 which is used as a control signal. When the control signal is“1”, the selector 56 selects the output of the AND circuit 55. When thecontrol signal is “0”, the selector 56 selects the output of the ORcircuit 52. The AND circuit 57 receives the output of the selector 56and the output of a corresponding bit of the state transition circuit51. The output of the AND circuit 57 is the output of the logic circuit53. The AND circuit 58 receives the output of a corresponding bit of thestate transition circuit 51 as an A-terminal input and the output of abit immediately previous to the corresponding bit as a B-terminal input.The output of the AND circuit 58 functions as a control signal of theselector 56. In the logic circuit 53 to which the least significant bitC₁ is input at the A-terminal, “0” (ground potential) is input at theB-terminal.

[0058] The D-type flip flop circuit 54 of the input control circuit 30receives the least significant bit C₁ of the state transition circuit 51as a data input and clock signal CK from the frequency comparator 7 as aclock input.

[0059] In the input control circuit 30, the most significant bit I_(n+1)is used as a sign bit. At the most significant bit I_(n+1) and bitI_(n), the DOWN signal is output as it is. Outputs I_(n−1), I_(n−2), . .. , and I₁ of the (N−1)th and subsequent bits are the outputs of thecorresponding logic circuits 53.

[0060] Next, an operation of the dual loop PLL of the present embodimentis described. The entire operation of the dual loop PLL of the presentembodiment is substantially the same as that of the conventionaltechnique. Thus, only an operation performed in the frequency comparisonmode with the frequency comparison loop, which is a characteristicfeature of the present invention, is described.

[0061] In the frequency comparator 7, one of external reference clockCLex (10) and internal clock CLin (11) which has the higher frequencychanges the most significant bit of the counter 40 of the clock counterof FIG. 2 to “1” prior to the other one. Thus, in the case where thefrequency of external reference clock CLex (10) is higher than that ofinternal clock CLin (11), the UP signal is output prior to the DOWNsignal. In the case where the frequency of internal clock CLin (11) ishigher than that of external reference clock CLex (10), the DOWN signalis output prior to the UP signal. As shown in FIG. 2, signal CKO (46)output from each of the clock counters 20 and 21 is AND logic of themost significant bit and the least significant bit of the counter 40.Thus, signal CKO (46) is output at the time delayed by one period of asignal input at the CK terminal 43 from the time when C-signal (UPsignal or DOWN signal) is output. Clock signal CK output from thefrequency comparator 7 is OR logic of output signals CKO (46) of theclock counters 20 and 21. Thus, if the UP signal is output prior to theDOWN signal, clock signal CK is output after one period of externalreference clock CLex (10) has passed. If the DOWN signal is output priorto the UP signal, clock signal CK is output after one period of internalclock CLin (11) has passed.

[0062] Since signal NRO (47) of each of the clock counters 20 and 21 isthe output of the D-type flip flop circuit 42 as shown in FIG. 2, signalNRO (47) is output at the time delayed by one period of the clock signalinput to the CK terminal 43 from the time when signal CKO (46) isoutput. Each of the signals NRO (47) is input to the AND circuit 23 andresets the clock counter 20 or 21 itself.

[0063] In summary, the frequency comparator 7 outputs the UP signal orDOWN signal and outputs clock signal CK one period after the UP signalor DOWN signal is output (one period is a period of one of externalreference clock CLex (10) and internal clock CLin (11) which has thehigher frequency). Reset signal NRO (47) is output one period afterclock signal CK is output (one period is a period of one of externalreference clock CLex (10) and internal clock CLin (11) which has thehigher frequency), thereby resetting the clock counters 20 and 21 for anew frequency comparison.

[0064] The operation of the frequency comparator 7 is repeated until theinputs to the clock counters 20 and 21 are interrupted by frequencycoincidence signal FSTOP input from the up/down counter 8.

[0065] Operation of Up/Down Counter

[0066] In the up/down counter 8, the adder 31 adds the output of theinput control circuit 30 (a ½ value of the previous addition/subtractionresult value) to the output of the register 33 which stores the countvalue. The result of the addition is latched by the register 33 when theregister 33 receives clock signal CK from the OR circuit 22 of thefrequency comparator 7.

[0067] The outputs of the input control circuit 30 of the up/downcounter 8 is now described. Among n−1 logic circuits 53, i.e., among thelogic circuits 53 corresponding to bits I₁ to I_(n−1) of the inputcontrol circuit 30, a logic circuit 53 in which the level of A-terminalof the AND circuit 58 is “1” and the level of B-terminal of the ANDcircuit 58 is “0” outputs “1” when any of the UP signal and DOWN signalis “1”. A logic circuit 53 in which the levels of A-terminal andB-terminal of the AND circuit 58 are both “1” outputs “0” when only theUP signal is “1” and outputs “1” when only the DOWN signal is “1”. Alogic circuit 53 in which the levels of A-terminal and B-terminal areboth “0” outputs “0” irrespective of the values of the UP signal andDOWN signal. When the state transition circuit 51 is in the initialstate immediately after being reset (i.e., the state where only the mostsignificant bit C_(n−1) is “1” and the other bits are “0”), bit I_(n−1)is “1”, the bits lower than bit I_(n−1) are all “0”, and the bits higherthan bit I_(n−1), i.e., bit I_(n) and bit I_(n+1), are “0” when the UPsignal is input to the input control circuit 30 but “1” when the DOWNsignal is input to the input control circuit 30. That is, in the initialstate, as for the output of the input control circuit 30, the bitsI_(n+1) to I₁ are “0010.0” when the UP signal is “1”, but the bitsI_(n+1) to I₁ are “1110 . . . 0” when the DOWN signal is “1”.

[0068] Thereafter, when clock signal CK of the frequency comparator 7 isinput to the input control circuit 30, the state transition circuit 51transitions to a next state where the output state is such that bitC_(n−1) and bit C_(n−2) are “1”, and bit C_(n−3) and subsequent bits are“0”. In this state, the output of the input control circuit 30 is “00010. . . 0” when the UP signal is “1” but “11110 . . . 0” when the DOWNsignal is “1”.

[0069] Subsequent states where subsequent clock signals CK are input tothe input control circuit 30 are now described likewise. Every timeclock signals CK is input, the absolute value of the output value of theinput control circuit 30 changes from the initial state to a ¼ of themaximum value 2^(N) of the up/down counter 8, a ⅛ of 2^(N) (i.e., a ½ ofthe previous addition/subtraction result value), a {fraction (1/16)} of2^(N) (i.e., a ½ of the previous addition/subtraction result value), . .. , and “1”. The output of the input control circuit 30 is a positivevalue when the UP signal is input, but a negative value when the DOWNsignal is input.

[0070] Herein, the absolute value in the initial state is not a ½ but a¼ of the maximum value 2^(N), because the value of the register 33 isset to a ½ of the maximum value 2^(N) in the initial state.

[0071] Thus, after a frequency comparison is performed by the frequencycomparator 7, the UP signal or DOWN signal is input to the up/downcounter 8. When the UP signal is input, the output value of the inputcontrol circuit 30 is a positive value of a ½ of the previousaddition/subtraction result value. When the DOWN signal is input, theoutput value of the input control circuit 30 is a negative value of a ½of the previous addition/subtraction result value. The output value ofthe input control circuit 30 is added to the count value of the register33, and the result of addition is input to the register 33 again. Theregister 33 receives from the frequency comparator 7 clock signal CK atthe time delayed by one period (this “one period” is a period of one ofexternal reference clock CLex (10) and internal clock CLin (11) whichhas the higher frequency) from the time when the UP signal or DOWNsignal is output from the frequency comparator 7. At the time of receiptof clock signal CK, the register 33 latches the addition/subtractionresult value of the adder 31. Thus, when the UP signal is input to theup/down counter 8, the count value of the up/down counter 8 increases bya ½ of the previous addition/subtraction result value. When the DOWNsignal is input to the up/down counter 8, the count value of the up/downcounter 8 decreases by a ½ of the previous addition/subtraction resultvalue.

[0072] Thereafter, in the frequency comparator 7, reset signal NRO (47)is output from the clock counter 20 or 21 at the time delayed by oneperiod (a period of one of external reference clock CLex (10) andinternal clock CLin (11) which has the higher frequency) from the timewhen clock signal CK is output, and the clock counters 20 and 21themselves are reset.

[0073] In response to a change in the count value of the up/down counter8, the VCO characteristic control circuit 9 changes the V-Fcharacteristic of the voltage controlled oscillator 5 according to thecount value. As a result, the output frequency of the voltage controlledoscillator 5 is changed, and internal clock CLin (11) which is generatedby dividing the output frequency of the voltage controlled oscillator 5by the frequency divider circuit 6 is also changed.

[0074] In this way, in the frequency comparison loop, the frequencycomparison of external reference clock CLex (10) with changed internalclock CLin (11) is carried out in the frequency comparator 7. Accordingto the result of the comparison, the count value of the up/down counter8 is incremented or decremented by a ½ of the previous count value. Sucha frequency comparison operation based on a dichotomizing search methodis repeated.

[0075] Then, in the state transition circuit 51 of the input controlcircuit 30 of the up/down counter 8, when clock signal CK is input fromthe frequency comparator 7 to the input control circuit 30 under thestate where the least significant bit C₁ is “1” (i.e., the state wherethe up/down counter 8 is in the final step interval), the frequencycomparison stop signal 16 output from the D-type flip flop circuit 54 ofthe input control circuit 30 is “1”, and this signal 16 is input to thefrequency comparator 7 and the operation mode switch 3. Therefore, theoperation of the frequency comparator 7 is stopped, while the operationmode switch 3 is switched from the F-side to the P-side. As a result,the frequency comparison mode is ended, while the loop is switched tothe phase comparison loop so that the phase comparison mode is selected.

[0076] As described above, according to the present embodiment, afrequency comparison based on a dichotomizing search method can beperformed in a dual loop PLL. Thus, the frequency comparison operationis performed at a higher speed and with greater efficiency, and the lockup time is reduced, as compared with a conventional dual loop PLLincluding an up/down counter which operates on a step by step basis. Forexample, in the case where the number of bits of the up/down counter 8is “3”, the frequency comparison is required 8 times at maximum in aconventional technique. However, the present embodiment requires thefrequency comparison only 3 times.

[0077] (Embodiment 2)

[0078] Next, a dual loop PLL of embodiment 2 of the present invention isdescribed.

[0079] In the above-described dual loop PLL of embodiment 1, a frequencycomparison is performed based on a dichotomizing search method. In thecase of a frequency comparison loop, the absolute value of a variationin the frequency of the voltage controlled oscillator 5 is moderatelydecreased on a half-step by half-step basis. Thus, the frequencycomparison accuracy required of the frequency comparator 7 can bedecreased more at earlier steps of the frequency comparison. However, inthe clock counter 20 of FIG. 2 which is included in the frequencycomparator 7 of embodiment 1, the frequency comparison is performedalways with the same frequency comparison accuracy (specifically, basedon the count number of clock CK (43) in the clock counter 20) throughoutthe earlier steps (start period), intermediate steps, and final steps ofthe frequency comparison. Thus, in the earlier steps immediately afterthe start of the frequency comparison, the frequency comparison isperformed with accuracy higher than necessary, i.e., an unnecessaryfrequency comparison time is consumed.

[0080] In view of such, according to embodiment 2, the clock counter 20of FIG. 2 is improved such that the frequency comparison accuracy isvariable. With such an improvement, the frequency comparison accuracy isadjusted to the least necessary level for the earlier steps,intermediate steps, and final steps of the frequency comparison, wherebythe frequency comparison time is further reduced, and the lock up timeis decreased.

[0081]FIG. 4 shows a specific structure of a clock counter 20′ includedin a frequency comparator 7 of a dual loop PLL of embodiment 2.

[0082] The clock counter 20′ of FIG. 4 includes an accuracy varyingcircuit 59 for varying the frequency comparison accuracy for respectivesteps of the dichotomizing search process of the frequency comparison.The accuracy varying circuit 59 receives output signals C_(n−1),C_(n−2), . . . , and C₁ of n−1 bits which are output from the statetransition circuit 51 of the input control circuit 30 shown in FIG. 3.The accuracy varying circuit 59 includes two-input exclusive OR circuits50(n−1), 50(n−2), . . . , and 50(1) up to the number equal to the numberof bits of the output signals (=n−1), and the same number of two-inputAND circuits 49(n−1), 49(n−2), . . . , and 49(1), and one OR circuit 48.On the other hand, a counter 40′ is formed by a m-bit counter (m is apositive value greater than n).

[0083] In the accuracy varying circuit 59, each of the exclusive ORcircuits 50(n−1) to 50(2) receives the output of a corresponding bit ofthe state transition circuit 51 and the output of a bit immediatelyprevious to the corresponding bit. The value “0” (ground potential) isinput to the exclusive OR circuit 50(1) which receives output C₁ of theleast significant bit of the state transition circuit 51. Each of theAND circuits 49(n−1) to 49(1) receives the output of a corresponding oneof the exclusive OR circuits 50(n−1) to 50(1). The n−1 AND circuits49(n−1) to 49(1) correspond to the n−1 higher bits of the counter 40′,i.e., bits Am-(n−1) to Am, and receives the output of correspondingbits. Specifically, the output of bit Am-(n−1) of the counter 40′ isinput to the AND circuit 49(n−1) corresponding to the most significantbit, and the output of the most significant bit Am of the counter 40′ isinput to the AND circuit 49(1) corresponding to the least significantbit. The outputs of the AND circuits 49(n−1) to 49(1) are input to theOR circuit 48, and the output of the OR circuit 48 is the C-signal (45)output from the frequency comparator 7 (UP signal or DOWN signal).

[0084] Thus, according to embodiment 2, outputs C_(n−1) to C₁ of thestate transition circuit 51 subsequently change at every frequencycomparison step (i.e., at every output of the UP signal or DOWN signalfrom the clock counter 20′), from the initial reset state, i.e., “100 .. . 0”, to “110 . . . 0”, and “111 . . . 0”, finally resulting in “111 .. . 1”. Thus, the combination of the outputs of the exclusive ORcircuits 50(n−1) to 50(1) changes from the initial reset state to “100 .. . 0”, “010 . . . 0”, . . . , and finally resulting in “000 . . . 1”.As a result, at the first step of the frequency comparison, the outputof the AND circuit 49(n−1) corresponding to the most significant bitbecomes High according to the output of bit Am-(n−1) of the counter 40′,so that the OR circuit 48 outputs the C-signal (45) (UP signal or DOWNsignal). Then, at the second step, the C-signal (45) (UP signal or DOWNsignal) is output for a bit at a one bit higher place of the counter40′, i.e., bit Am-(n−2). Then, at the third step, the C-signal (45) (UPsignal or DOWN signal) is output for a bit at a one bit higher place ofthe counter 40′, i.e., bit Am-(n−3). Then, at the final step, the outputof the AND circuit 49(1) at the least significant bit becomes Highaccording to the output of the most significant bit Am of the counter40′, so that the C-signal (45) (UP signal or DOWN signal) is output fromthe OR circuit 48.

[0085] Thus, every time the frequency comparison proceeds by one step,the number of counts which is used for the frequency comparison isdoubled, and accordingly, the frequency comparison accuracy increases bya factor of 2. Explaining in view of the opposite direction, thecomparison accuracy decreases stepwise by a factor of 2 toward theearlier steps of the frequency comparison. Therefore, the accuracy ismade lower at the earlier steps of the frequency comparison by using thefrequency comparator 7 which includes the clock counter 20′ ofembodiment 2. Therefore, the frequency comparison accuracy is adjustedto the least necessary level at each step of the frequency comparison,such that the frequency comparison is performed more efficiently.

[0086] (Embodiment 3)

[0087] Next, a dual loop PLL of embodiment 3 of the present invention isdescribed.

[0088]FIG. 5 shows an internal structure of an input control circuit ofan up/down counter included in the dual loop PLL of embodiment 3. Theinternal structure of the up/down counter and the other componentsincluding a frequency comparator, and the like, are the same as those ofthe dual loop PLL of embodiment 1 except for the input control circuit,and descriptions and illustration thereof are herein omitted.

[0089] In the input control circuit 30 of embodiment 1 shown in FIG. 3,when both the UP signal and DOWN signal, which are output from thefrequency comparator 7, are “1” at the same time, the output of theinput control circuit 30 is the same as that output when only the DOWNsignal is input to the input control circuit 30, and in such a case, adown count (decrement) is erroneously performed. Before clock signal CKis output from the frequency comparator 7, the UP signal and DOWN signalare simultaneously input to the input control circuit 30 only when thefrequencies of external reference clock CLex (10) and internal clockCLin (11) are substantially equal. In this case, none of an up count(increment) or a down count (decrement) should be performed. Accordingto embodiment 3, an improvement is made to the input control circuit 30of FIG. 3 so as to overcome such a problem.

[0090] In FIG. 5, the input control circuit 30′ includes an error countprevention circuit 60, a D-type flip flop circuit 61 and an OR circuit66 in addition to the components of the input control circuit 30 of FIG.3 described in embodiment 1.

[0091] The error count prevention circuit 60 includes a NAND circuit 62and two AND circuits 63 and 64. The NAND circuit 62 receives the UPsignal and DOWN signal. The AND circuit 63 receives the DOWN signal andthe output of the NAND circuit 62 and outputs a DOWN′ signal. The ANDcircuit 64 receives the UP signal and the output of the NAND circuit 62and outputs an UP′ signal. With this arrangement, the error countprevention circuit 60 operates such that both the UP′ signal and DOWN′signal are “0” when both the UP signal and DOWN signal are “1” at thesame time.

[0092] The D-type flip flop circuit 61 receives as a data input a signalgenerated by inverting the output of the NAND circuit 62 by an inverter65, i.e., the logical product of the UP signal and DOWN signal. TheD-type flip flop circuit 61 further receives clock signal CK as a clockinput. The D-type flip flop circuit 61 latches the state where both theUP signal and DOWN signal are “1” to output a frequency coincidencesignal 67.

[0093] The OR circuit 66 receives the frequency coincidence signal 67from the D-type flip flop circuit 61 and an output signal 68 from thepreviously-described D-type flip flop circuit 54 (a signal output whenthe D-type flip flop circuit 54 operates at a final step interval) andoutputs frequency comparison stop signal FSTOP (16).

[0094] Thus, according to embodiment 3, before the end of the frequencycomparison based on a dichotomizing search method, in a frequencycoincidence state where the UP signal and DOWN signal are “1” at thesame time in the frequency comparator 7, the error count preventioncircuit 60 sets both the UP′ signal and DOWN′ signal to “0”. Thus, noneof an up count (increment) and a down count (decrement) is performed,whereby an error count is prevented.

[0095] The above frequency coincidence state is latched by the D-typeflip flop circuit 61 at the time when clock signal CK is output from thefrequency comparator 7, and the frequency coincidence signal 67 isoutput. Since the frequency comparison stop signal FSTOP (16) outputfrom the OR circuit 66 is the logical sum of the frequency coincidencesignal 67 and the signal 68 which is output from the D-type flip flopcircuit 54 when the D-type flip flop circuit 54 operates at the finalstep interval, frequency comparison stop signal FSTOP (16) is “1” whenthe frequency comparison based on a dichotomizing search method iscompleted or when the frequencies of external reference clock CLex (10)and internal clock CLin (11) are substantially equal. That is, accordingto embodiment 3, in the case where the frequencies becomes substantiallyequal in the midst of the dichotomizing search, and the UP signal andDOWN signal are simultaneously input before clock signal CK is inputfrom the frequency comparator 7, an error count in the up/down counter 8is prohibited, whereby the frequency comparison mode is stopped. Thus,the number of times of the frequency comparison is further reduced, andthe frequency comparison is performed more efficiently.

[0096] (Embodiment 4)

[0097] Next, a dual loop PLL of embodiment 4 of the present invention isdescribed.

[0098]FIG. 6 shows an internal structure of a frequency comparator 7′included in the dual loop PLL of embodiment 4. The components of thedual loop PLL of embodiment 4 are the same as those of the dual loop PLLof embodiment 1 except for the frequency comparator 7′, and thus,descriptions and illustration thereof are herein omitted.

[0099] In embodiment 1, when the count value of the up/down counter 8 ischanged in the frequency comparison loop so that the V-F characteristicof the voltage controlled oscillator 5 is shifted by the VCOcharacteristic control circuit 9, the output frequency of the voltagecontrolled oscillator 5 is transient until it becomes stationary, andaccordingly, internal clock CLin (11) which is generated by dividing theoutput frequency of the voltage controlled oscillator 5 by the frequencydivider circuit 6 is transient. Thus, in such a structure wherein thefrequency comparator 7 compares the transient frequency with thefrequency of external reference clock CLex (10), the frequencycomparison operation of the frequency comparator 7 is unstable.According to embodiment 4, the frequency comparison is forcedlyprohibited until the frequency of internal clock CLin (11) becomesstable.

[0100] Specifically, the frequency comparator 7′ of FIG. 6 includesthree AND circuits 70, 71 and 72, and a counter 73 in addition to thecomponents of the frequency comparator 7 shown in FIG. 1. The counter 73is reset based on reset signals NRO output from the clock counters 20and 21. After being reset, the counter 73 counts internal clock CLin(11), and when it reaches a predetermined count number, the counter 73changes the most significant bit C_(n) to “1”. The AND circuit 72receives internal clock CLin (11) and a MSB negation signal generated byinverting the most significant bit C_(n) of the counter 73 by aninverter 74. The output of the AND circuit 72 is input to the counter73. The AND circuit 70 receives external reference clock CLex (10) andthe most significant bit C_(n) of the counter 73. The output of the ANDcircuit 70 is input to the clock counter 20. The AND circuit 71 receivesinternal clock CLin (11) and the most significant bit C_(n) of thecounter 73. The output of the AND circuit 71 is input to the clockcounter 21.

[0101] Thus, according to embodiment 4, during a period when the V-Fcharacteristic of the voltage controlled oscillator 5 is shifted so thatthe output frequency of the voltage controlled oscillator 5 istransient, i.e., until the counter 73 counts internal clock CLin (11) upto a predetermined clock number, the frequency comparison operation isnot performed in the frequency comparator 7′. Thereafter, the outputfrequency becomes stable, and at this point in time, external referenceclock CLex (10) and internal clock CLin (11) are input for the firsttime to the clock counters 20 and 21, respectively, and the frequencycomparison operation is started. Thus, the frequency comparison isperformed without the influence of transient internal clock CLin (11)which occurs when the V-F characteristic of the voltage controlledoscillator 5 is shifted.

[0102] (Embodiment 5)

[0103] Next, a dual loop PLL of embodiment 5 of the present invention isdescribed.

[0104] In the dual loop PLL of embodiment 1 shown in FIG. 1, when thefrequency comparison mode is selected, the operation mode switch 3 isswitched to the F-side to supply reference voltage Vref (15) to the loopfilter 4, whereby a predetermined voltage is supplied as the inputvoltage to the voltage controlled oscillator 5. In this structure, theloop filter 4 is a load on a circuit for generating reference voltageVref (15). Thus, it takes a certain time until the voltage input to thevoltage controlled oscillator 5 reaches a predetermined voltage, and asa result, it takes a certain time until the output of the voltagecontrolled oscillator 5 becomes stable. In embodiment 5, an improvementis made to the circuit structure of the dual loop PLL of FIG. 1 in orderto overcome such an inconvenience.

[0105]FIG. 7 shows a structure of a dual loop PLL of embodiment 5. Thedual loop PLL shown in FIG. 7 is different from that of embodiment 1shown in FIG. 1 in that the position of the operation mode switch 3 ischanged to a stage subsequent to the loop filter 4, and that a referencevoltage circuit 17 and a switch 18 are further provided. The othercomponents, e.g., the frequency comparator 7, and the like, are the sameas those of the dual loop PLL of embodiment 1, and therefore,descriptions and illustration thereof are herein omitted.

[0106] In FIG. 7, the reference voltage circuit 17 generates referencevoltage Vref (15), which is supplied to the F-side of the operation modeswitch 3 and to the loop filter 4 through the switch 18. The switch 18is ON (closed) in the frequency comparison mode but is OFF (open) in thephase comparison mode.

[0107] In FIG. 7, the operation mode switch 3 is switched to the F-sidewhen the frequency comparison mode is selected, so that the loop filter4 placed at the stage previous to the voltage controlled oscillator 5 isdisconnected from the voltage controlled oscillator 5, and referencevoltage Vref (15) having a predetermined value, which is generated bythe reference voltage circuit 17, is directly supplied as the inputvoltage to the voltage controlled oscillator 5. Thus, comparing with thedual loop PLL shown in FIG. 1, the loop filter 4 does not constitute theload on the reference voltage circuit 17. That is, the load on thereference voltage circuit 17 is reduced. Therefore, according toembodiment 5, the voltage input to the voltage controlled oscillator 5quickly reaches the level of reference voltage Vref (15). As a result,the transient variation time of the output frequency of the voltagecontrolled oscillator 5 at the initial operation steps is reduced, andthe influence of the transient state at the initial operation steps onthe frequency comparison is reduced.

[0108] In the frequency comparison mode, the switch 18 is turned ON(closed) so that the loop filter 4 disconnected from the voltagecontrolled oscillator 5 is connected to the reference voltage circuit17. Thus, reference voltage Vref (15), which is at the same level asthat of the voltage input to the voltage controlled oscillator 5, issupplied to the loop filter 4, and the voltage level of the loop filter4 reaches the level of reference voltage Vref (15) within the frequencycomparison mode period.

[0109] Thereafter, the dual loop PLL transitions to the phase comparisonmode, the switch 18 is turned OFF (open), so that the loop filter 4 isdisconnected from the reference voltage circuit 17. The loop filter 4 isconnected to the voltage controlled oscillator 5 by switching theoperation mode switch 3 to the P-side. Therefore, in embodiment 5, thevoltage input to the voltage controlled oscillator 5 does not vary evenwhen the dual loop PLL transitions from the frequency comparison mode tothe phase comparison mode. Thus, it is possible to immediately start thephase comparison even at the time when the frequencies of externalreference clock CLex (10) and internal clock CLin (11) are substantiallyequal. Therefore, even when the loop filter 4 is disconnected from theinput side of the voltage controlled oscillator 5 in the frequencycomparison mode, and reference voltage Vref (15) is supplied to theinput side of the voltage controlled oscillator 5, the dual loop PLLsmoothly transitions to the phase comparison mode, and the time spentfor the frequency comparison is efficiently decreased.

[0110] (Embodiment 6)

[0111] Next, a dual loop PLL according to embodiment 6 of the presentinvention is described.

[0112] Embodiment 6 intends to make a modification to embodiment 1 shownin FIG. 1 such that, in the case where reference voltage Vref (15)deviates from a predetermined value due to variations in a productionprocess of the reference voltage circuit 17, or the like, the voltagewhich is input to the voltage controlled oscillator 5 during the dualloop PLL being locked is prevented from excessively increasing ordecreasing.

[0113]FIG. 8 shows an internal structure of an input control circuit 30″included in an up/down counter 8 of a dual loop PLL of embodiment 6. Theinternal structure of the up/down counter 8 and the other components,e.g., the frequency comparator 7, and the like, are the same as those ofthe dual loop PLL of embodiment 1 except for the input control circuit30″, and therefore, descriptions and illustration thereof are hereinomitted.

[0114] In FIG. 8, the input control circuit 30″ includes a priorityswitch circuit 80 in addition to the input control circuit 30 of FIG. 3which has been described in embodiment 1.

[0115] The priority switch circuit 80 includes a NAND circuit 81, two ORcircuits 82 and 83, and two AND circuits 84 and 85. The priority switchcircuit 80 receives DOWN priority signal PDN and UP priority signal PUP.The NAND circuit 81 receives the DOWN signal and UP signal from thefrequency comparator 7 shown in FIG. 1. The OR circuit 82 receives theoutput of the NAND circuit 81 and DOWN priority signal PDN. The ORcircuit 83 receives the output of the NAND circuit 81 and UP prioritysignal PUP. The AND circuit 84 receives the output of the OR circuit 82and the DOWN signal, and outputs a DOWN′ signal. The AND circuit 85receives the output of the OR circuit 83 and the UP signal, and outputsan UP′ signal.

[0116] In the priority switch circuit 80 having the above structure, ifthe frequencies of external reference clock CLex (10) and internal clockCLin (11) come close to each other so that the DOWN signal and UP signalare simultaneously input from the frequency comparator 7 to the priorityswitch circuit 80, i.e., the frequencies of external reference clockCLex (10) and internal clock CLin (11) (reference frequency and outputfrequency) are equal, the output of the NAND circuit 81 is Low. If theUP signal is required to have priority over the DOWN signal, UP prioritysignal PUP is set to High and DOWN priority signal PDN is set to Low.Accordingly, the UP′ signal becomes High and the DOWN′ signal becomesLow, so that the UP signal has priority over the DOWN signal. On theother hand, if the DOWN signal is required to have priority over the UPsignal, DOWN priority signal PDN is set to High and UP priority signalPUP is set to Low. Accordingly, the DOWN′ signal becomes High and theUP′ signal becomes Low, and thus, the DOWN signal has priority over theUP signal.

[0117] In the case where monitored reference voltage Vref (15) becomeshigher than the predetermined voltage due to variations in theproduction process, the priority switch circuit 80 gives priority to theUP signal, whereby the frequency of internal clock CLin (11) is higherthan that of external reference clock CLex (10) at the end of thefrequency comparison. Thus, in the phase comparison subsequentlyperformed, the voltage input to the voltage controlled oscillator 5 suchthat decrease the frequency of internal clock CLin (11) is decreased. Inthe end, the voltage which is input to the voltage controlled oscillator5 during the dual loop PLL being locked decreases to a voltage levellower than increasingly deviated reference voltage Vref (15), which issubstantially equal to the predetermined value. Alternatively, in thecase where monitored reference voltage Vref (15) becomes lower than thepredetermined voltage, the priority switch circuit 80 gives priority tothe DOWN signal, whereby the voltage which is input to the voltagecontrolled oscillator 5 during the dual loop PLL being locked increasesto a voltage level higher than decreasingly deviated reference voltageVref (15), which is substantially equal to the predetermined value.

[0118] Thus, according to embodiment 6, even when reference voltage Vref(15) deviates from the predetermined voltage due to process variations,the priority switch circuit 80 gives priority to the UP signal or DOWNsignal, whereby the voltage which is input to the voltage controlledoscillator 5 during the dual loop PLL being locked is prevented fromexcessively increasing or decreasing. Thus, reference voltage Vref (15)is adjusted to a desired voltage level having desirable characteristics.

[0119] (Embodiment 7)

[0120] Next, a dual loop PLL according to embodiment 7 of the presentinvention is described.

[0121]FIG. 9 shows an internal structure of a charge pump 2 included inthe dual loop PLL of embodiment 7. FIG. 10 shows an entire structure ofthe dual loop PLL including the charge pump 2.

[0122] In the dual loop PLL of FIG. 10, the charge pump 2 is placed at astage subsequent to the phase comparator 1 and has the internalstructure shown in FIG. 9. The charge pump 2 includes two OR circuits 91and 92, a Pch transistor 93 for determining a charging current of thecharge pump 2, a Nch transistor 94 for determining a discharging currentof the charge pump 2, and two switches 95 and 96. The gate voltages ofthe Pch transistor 93 and Nch transistor 94 are biased such that thecharging current and the discharging current of the charge pump 2becomes equal to each other.

[0123] The two OR circuits 91 and 92 receive frequency comparison stopsignal FSTOP (16) from the up/down counter 8 through an inverter 90. TheOR circuit 91 receives the UP signal from the phase comparator 1. The ORcircuit 92 receives the DOWN signal from the phase comparator 1: Theswitch 95 is controlled according to the output of the OR circuit 91 tointerrupt the charging current. The switch 96 is controlled according tothe output of the OR circuit 92 to interrupt the discharging current.

[0124] In the charge pump 2 of embodiment 7, when the frequencycomparison mode is selected, i.e., when frequency comparison stop signalFSTOP (16) is “0”, both the switches 95 and 96 are ON (closed), so thata voltage which is about a ½ of the supply voltage is output asreference voltage Vref from output terminal CPout. This referencevoltage Vref is input to the loop filter 4.

[0125] On the other hand, consider a case where frequency comparisonstop signal FSTOP (16) is changed to “1” so that the dual loop PLLtransitions to the phase comparison mode. When the UP signal is inputfrom the phase comparator 1, only the switch 95 is turned ON so that thecharging operation is performed. When the DOWN signal is input from thephase comparator 1, only the switch 96 is turned ON so that thedischarging operation is performed.

[0126] Thus, the dual loop PLL of embodiment 7 has the function of anoperation mode switch in the charge pump 2. Therefore, as seen fromcomparison of FIG. 10 of embodiment 7 and FIG. 1, the operation modeswitch 3 and reference voltage Vref (15) may be omitted. Thus, in thedual loop PLL of embodiment 7, the operation mode switch 3 and thereference voltage circuit for generating reference voltage Vref (15),which have been shown in FIG. 1, may be omitted, and the effects ofreducing the circuit area and power consumption are achieved.

[0127] Embodiment 7 has been applied to the loop filter of the dual loopPLL shown in FIG. 1. However, as a matter of course, the presentinvention may be applied to the charge pump of the conventional dualloop PLL shown in FIG. 13.

[0128] (Embodiment 8)

[0129] Next, a dual loop PLL according to embodiment 8 of the presentinvention is described.

[0130]FIG. 11(a) shows an internal structure of a loop filter 4 includedin the dual loop PLL of embodiment 8. The components other than the loopfilter 4 are the same as those of the dual loop PLL of embodiment 1, andtherefore, descriptions and illustration thereof are herein omitted.

[0131] A structure of the loop filter 4 described in embodiment 8 issuitable for the dual loop PLL quickly recovering from a power down mode(i.e., operation mode wherein the operation is stopped to suppress powerconsumption) to the normal operation.

[0132] In FIG. 11(a), the loop filter 4 includes a terminal 100connected to the output side of the charge pump 2 and the input side ofthe voltage controlled oscillator 5 (see FIG. 1), a resistor 101 one endof which is connected to the terminal 100, and a Nch-type transistor 102and a Pch-type transistor 103 whose gate terminals are connected to theother end of the resistor 101. The Nch-type transistor 102 has a sourceterminal, a drain terminal and a bulk terminal which are connected tothe ground. The Pch-type transistor 103 has a source terminal, a drainterminal and a bulk terminal which are connected to the power supplyVcc.

[0133] A structure of a conventional loop filter is shown in FIG. 11(b).This conventional loop filter 4 pr includes a terminal 100 which isconnected to the output side of the charge pump 2 and the input side ofthe voltage controlled oscillator 5 (see FIG. 1), and a resistor 101 anda Nch-type transistor 106 which are placed between the terminal 100 andthe ground. The MOS capacitance of the Nch-type transistor 106constitutes the capacitance of the loop filter 4 pr.

[0134] In the conventional loop filter 4 pr, in the power down mode, thepotential of the terminal 100 of the loop filter 4 pr decreases with thepassage of time due to influence of a leaked current from the Nch-typetransistor 106. Thus, when the dual loop PLL transitions from the powerdown mode to the normal operation, a certain time is spent until thedual loop PLL is locked because the oscillation frequency of the voltagecontrolled oscillator 5 decreases due to a decrease in the potential ofthe loop filter 4 pr. Moreover, when the loop filter 4 pr operates witha low supply voltage, the voltage range of the supply voltage is suchthat a variation in the MOS capacitance in the loop filter 4 pr is largewith respect to the bias voltage as shown in FIG. 12(b). Thus, in such acase, it is difficult to appropriately design the dual loop PLL.

[0135] On the other hand, in the loop filter 4 of embodiment 8, even inthe presence of a leaked current flowing from the Nch-type transistor102 to the ground, the leaked current is cancelled by a leaked currentflowing from the Pch-type transistor 103 connected to the supply voltageVcc to the Nch-type transistor 102. Thus, the potential of the terminal100 of the loop filter 4 is unlikely to decrease. Therefore, in the loopfilter 4 of embodiment 8, the potential of the terminal 100 of the loopfilter 4 is kept at a generally constant potential for a long time inthe power down mode as compared with the conventional loop filter 4 pr.As a result, when the dual loop PLL transitions from the power down modeto the normal operation, the loop filter 4 can be locked within a shortperiod of time as compared with the conventional loop filter 4 pr.

[0136] Furthermore, in the loop filter 4 of embodiment 8, thecapacitance of the loop filter 4 is a combined capacitance of the MOScapacitance of the Nch-type transistor 102 and the MOS capacitance ofthe Pch-type transistor 103 as shown in FIG. 12(a). Thus, a variation inthe combined MOS capacitance with respect to the bias voltage is reducedto a half of the capacitance variation of the conventional loop filter 4pr shown in FIG. 12(b).

[0137] Embodiment 8 has been applied to the loop filter 4 of the dualloop PLL shown in FIG. 1. However, as a matter of course, the presentinvention may be applied to the loop filter of the conventional dualloop PLL shown in FIG. 13 or a loop filter included in a single looptype PLL.

INDUSTRIAL APPLICABILITY

[0138] As described above, in a dual loop PLL of the present invention,the frequency comparison in a frequency comparison loop is performedbased on a dichotomizing search method. Thus, the frequency comparisonis efficiently performed, and the lock up time is effectively reduced.Further, time reduction is possible when it is necessary to increase theoutput frequency up to the maximum frequency. Therefore, it ispreferable that the present invention is applied to a dual loop PLL.

[0139] According to the present invention, the frequency comparison inthe frequency comparison loop is performed based on a dichotomizingsearch method, and the frequency comparison accuracy is variable forrespective steps of the frequency comparison along with the progress ofthe dichotomizing search. The time required for the frequency comparisonin each step can be reduced, and the lock up time can be furtherreduced. Thus, it is preferable that the present invention is applied toa dual loop PLL.

[0140] According to the present invention, when the output frequency isequal to the reference frequency before the frequency comparison basedon the dichotomizing search method is not completed, none of an up count(increment) and a down count (decrement) of a count value in an up/downcounter is forcedly prohibited, whereby an error count is prevented.Moreover, at this point in time, the frequency comparison mode can beended at earlier steps. Thus, it is preferable that the presentinvention is applied to a dual loop PLL.

[0141] In addition, according to the present invention, the frequencycomparison is not performed during the period when a voltage controlledoscillator controls a variation in the output frequency. Thus, thefrequency comparison is always performed with the stable outputfrequency and the reference frequency, and a desirable frequencycomparison is secured. Thus, it is preferable that the present inventionis applied to a dual loop PLL.

[0142] According to the present invention, when the frequency comparisonloop is formed, the reference voltage of a reference voltage circuit isdirectly supplied to the voltage controlled oscillator. Thus, the loopfilter does not constitute a load, and the load on the reference voltagecircuit is reduced. Moreover, when the frequency comparison loop isformed, the reference voltage of the reference voltage circuit is alsosupplied to the loop filter. Therefore, transition from the frequencycomparison loop to the phase comparison loop is smoothly achieved, andthe time required for the phase comparison can be reduced. Thus, it ispreferable that the present invention is applied to a dual loop PLL.

[0143] According to the present invention, even when the referencevoltage supplied to the voltage controlled oscillator deviates from apredetermined value due to variations in the production process, apriority switch circuit give priority to a UP signal or DOWN signal,whereby the voltage which is input to the voltage controlled oscillatorduring the PLL being locked is adjusted to a desirable reference voltagelevel. Thus, it is preferable that the present invention is applied to adual loop PLL.

[0144] In addition, according to the present invention, the function ofan operation mode switch, which switches the operation mode between thefrequency comparison mode and the phase comparison mode, and thefunction of a reference voltage generation circuit are realized by acharge pump. Accordingly, the structure of the dual loop PLL issimplified. Thus, it is preferable that the present invention is appliedto a dual loop PLL.

[0145] According to the present invention, a P-type transistor isprovided in the loop filter in addition to a N-type transistor. In thepower down mode, a leaked current flowing from the N-type transistor tothe ground is cancelled by a leaked current flowing from the P-typetransistor to the N-type transistor. Thus, the potential of the loopfilter is maintained at a substantially constant potential for a longtime period. After the PLL transitions from the power down mode to thenormal operation, locking of the PLL can be achieved within a short timeperiod. Moreover, a voltage variation is restricted to a small variationas compared with a conventional loop filter. Thus, it is preferable thatthe present invention is applied to a dual loop PLL.

1. A dual loop PLL, comprising: a frequency comparison loop whichincludes a frequency comparator and a phase comparison loop whichincludes a phase comparator, wherein in the frequency comparison loop, afrequency comparison between a reference frequency and an outputfrequency is performed based on a dichotomizing search method.
 2. A dualloop PLL according to claim 1, wherein: the frequency comparison loopincludes the frequency comparator, an up/down counter for incrementingor decrementing a count value according to a comparison result from thefrequency comparator, and a voltage controlled oscillator for changingthe output frequency according to the count value of the up/downcounter; and the up/down counter includes a register for storing thecount value, an input control circuit for outputting a positive ornegative value of a ½ of a previous addition/subtraction result valueaccording to the comparison result from the frequency comparator, and anadder for adding the count value of the register to the output of theinput control circuit.
 3. A dual loop PLL according to claim 2, whereinthe frequency comparator includes an accuracy varying circuit forvarying a frequency comparison accuracy for respective steps of thefrequency comparison along with the progress of the dichotomizingsearch.
 4. A dual loop PLL according to claim 2, wherein: the frequencycomparator is structured such that if the output frequency is equal toor lower than the reference frequency, the frequency comparator outputsan UP signal, and if the output frequency is equal to or higher than thereference frequency, the frequency comparator outputs an DOWN signal;and the up/down counter includes an error count prevention circuit forprohibiting an increment or decrement of the count value when the UPsignal and DOWN signal are simultaneously received from the frequencycomparator.
 5. A dual loop PLL according to claim 2, wherein thefrequency comparator avoids comparing a transient frequency, whichoccurs during the period when the voltage controlled oscillator controlsa variation in the output frequency, with the reference frequency.
 6. Adual loop PLL according to claim 1, wherein: the phase comparison loopincludes a voltage controlled oscillator, and a loop filter placed at astage previous to the voltage controlled oscillator; and when thefrequency comparison loop is formed, the loop filter is disconnectedfrom the voltage controlled oscillator, and a reference voltage having apredetermined value is supplied to the loop filter and the voltagecontrolled oscillator.
 7. A dual loop PLL according to claim 2, wherein:when the frequency comparison loop is formed, the voltage controlledoscillator receives a reference voltage having a predetermined value;and the up/down counter includes a priority switch circuit whichreceives a comparison result from the frequency comparator and, if thereference frequency and the output frequency are equal to each other,priorly increments or decrements a count value according to a variationof the reference voltage from the predetermined value.
 8. A dual loopPLL according to claim 1, further comprising: a charge pump placed at astage subsequent to the phase comparator; a loop filter which is chargedand discharged by the charge pump; and a voltage controlled oscillatorto which an input voltage is supplied from the loop filter, wherein inthe frequency comparison mode, the charge pump supplies a referencevoltage having a predetermined value to the loop filter, and in thephase comparison mode, the charge pump charges or discharges the loopfilter according to an output of the phase comparator.
 9. A dual loopPLL according to claim 1, wherein: the phase comparison loop includes acharge pump placed at a stage subsequent to the phase comparator, a loopfilter placed at a stage subsequent to the charge pump; and the loopfilter includes a resistor having an end connected to the output side ofthe charge pump, and a N-type transistor and a P-type transistor whosegate terminals are connected to the other end of the resistor, whereinthe N-type transistor has a source terminal, a drain terminal and a bulkterminal which are connected to the ground, and the P-type transistorhas a source terminal, a drain terminal and a bulk terminal which areconnected to the power supply.